in this case the instruction set is extremely small (and includes open source verilog, so you could even fab it yourself)
quote from the website:
The CPU of the TKey is a modified version of PicoRV32, 32-bit RISC-V running at 18 MHz. Modifications includes a fast 32x32 multiplier implemented using the multiplier blocks in the iCE40 DSPs as well as a HW trap function.
The supported instruction set supported by the CPU is a subset of RV32I. Specifically it includes compressed instructions, but excludes instructions for:
Counters
System
Synch
CSR access
Change level
Trap redirect
Interrupt
MMU
The instruction set implemented by the CPU also includes multiplication instructions from the RV32IC_Zmmul (-march=rv32iczmmul) extension. Division is not supported.
Any illegal, unsupported instruction will halt the CPU. The halted CPU is detected by the hardware, which will blink the RGB LED with red to indicate the error state. There is no way for the CPU to exit the trap state besides a power cycle of the device.
Note that the CPU has no support for interrupts. No instructions, ports or logic.
in this case the instruction set is extremely small (and includes open source verilog, so you could even fab it yourself)
quote from the website:
https://developer.arm.com/documentation/dui0646/c/The-Cortex-M7-Instruction-Set/Instruction-set-summary
So is the Cortex M7. The entirety of the M0+, M4, and M7 microcontroller cores are very, very small ARMs.
Hmmm. Okay, so its an FPGA Risc-V then.
That’s kind of sad, that means there’s no hope that its as power-efficient as a proper ASIC core like ARM-M7.